Technical Field
The present invention generally relates to semiconductor devices, and more particularly, to measuring the width of a fin in a FinFET technology using a quantum well structure based on a measured peak tunneling current though the fin.
Background Information
In contrast to traditional planar metal-oxide-semiconductor, field-effect transistors (MOSFETs), which are fabricated using conventional lithographic fabrication methods, non-planar FET's incorporate various vertical transistor structures. One such semiconductor structure is the “FinFET”, which takes its name from the multiple semiconductor “fins” that are used to form the respective gate channels, and which are typically up to ten of nanometers in width. Advantageously, the fin structure helps to control current leakage through the transistor in the off stage, and a double gate or tri-gate structure may be employed to control short channel effects.
However, a variation in thickness of the semiconductor “fins” can affect the overall process stability and manufacturability, which in turn, can affect the semiconductor device performance and overall performance of the integrated circuit (IC). Currently, variation in thickness of the semiconductor “fins” is measured using an extensive fin measurement value data collection performed across the footprint of the semiconductor wafer or chip. However, due to vertical transistor structures of the semiconductor “fins”, such an application of data collection becomes limited, even more so as the semiconductor device fabrication processing transitions to smaller dimensions. Various other commonly employed optical measurement techniques such as, for example, transmission electron microscope, can be cost prohibitive and destructive.
Hence, there continues to be a need for a reliable, cost-effective method to measure the lateral thickness (also referred to as “width”) of semiconductor “fins”.